1. Field of the Present Invention
The present invention generally relates to the field of microprocessors and more particularly to the architectural state of a microprocessor and mechanisms for accessing and altering a microprocessor's state.
2. History of Related Art
Microprocessors include various internal facilities that enable the microprocessor to perform desired functions. These facilities include general purpose registers (GPRs), floating point registers (FPRs), and special purposes registers (SPRs). In addition to these architected facilities, microprocessors typically employ various internal registers, buffers, and other circuits to support the execution of instruction code. These facilities include, for example, the Next Instruction Address (NIA), which indicates the address of the next instruction to be fetched from instruction memory, various stacks that facilitate the execution of layered code (subroutines) and other features.
The values stored in all of these various registers at any one time are referred to as the microprocessor's state. Generally, a microprocessor's state information is not externally accessible. Although it would be theoretically possible to incorporate externally accessible signal pins, for example, to allow programmers, designers, test engineers, and others to determine a machine's state, the number of pins required to convey even a small portion of a device's state would greatly exceed the number of pins available in any packaging configuration.
To address this problem, the Joint Test Action Group (JTAG) standard, as specified in IEEE 1149.1, has been adopted by manufacturers of VLSI devices to provide a relatively simple means of accessing state information. As JTAG is implemented with respect to integrated circuits, a Test Access Port (TAP) employing four pins enables one to serially access or “long scan” at least some of a device's internal registers. In a “long scan” test, information is serially shifted along a series of predefined latches referred to as a scan chain. In this manner, information can be read from or written to these registers by clocking the desired data to or from the appropriate register. While the JTAG long scan mechanism is useful and relatively simple to implement into an integrated circuit design, its functionality is limited. Among the most significant limitations of conventional JTAG long scanning is the requirement to halt system clocks. Long scanning is achieved by incorporating an alternative path through the registers or latches in the scan chain. Data is shifted along the scan chain under control of a test clock. If the test clock and system clock(s) are running simultaneously, the state of the registers on the scan chain will be indeterminate. Halting system clocks is undesirable because substantially all systems associated with the microprocessor rely on the system clocks. When the system clocks are halted, the system is substantially shutdown thereby making it difficult to restart the system. It would be desirable to implement a mechanism that provided the internal access contemplated by JTAG without shutting down the system.